The present invention relates to a semiconductor device, and more particularly relates to a so-called masterslice semiconductor device.
In recent years a demand has arisen for fabrication of a large integrated semiconductor device which is suitable for low volume, wide variety manufacturing, without increasing the manufacturing cost and the manufacturing time. In response to this demand, the so-called masterslice semiconductor device has been proposed. In the usual masterslice semiconductor device, as is well known, first a large number of basic elements or regions are formed on a single semiconductor substrate; however, no interconnecting lines are formed between basic elements. Each of the cells is usually comprised of basic elements, such as transistors, resistors, diodes and so on. A semiconductor substrate comprised of only such basic elements is suitable for mass production. After mass production of the semiconductor substrate, the desired interconnecting lines between the basic elements and cells are then formed thereon by using specific masks for multilayer wiring, in accordance with a variety of large scale integrated circuits to be fabricated for obtaining respective desired logic circuits.
For the purpose of achieving a quick turnaround time and also reducing cost for manufacturing various kinds of, but small amounts of, LSIs, when compared to the above mentioned conventional masterslice LSI, the special masterslice LSI of the present invention is very useful.
In this special masterslice semiconductor device, since the basic cells, each comprising transistors, resistors, diodes, segments of interconnection metal lines of a lower metal layer and through holes, are originally mass produced in the semiconductor substrate, a desired device can be completed by, for example, simply preparing a specific mask for forming the desired interconnecting lines every time a need for obtaining certain logic circuits occurs. Accordingly, a reduction of the manufacturing time, or in other words quick turnaround time, can be achieved. Further, since the mass produced cells can be commonly utilized for obtaining any of the various kinds of logic circuits and most of the masks for producing the cells also can be commonly utilized for various cell types, thereby a reduction in manufacturing cost can be achieved.
However, the following requirements have arisen regarding the above mentioned special masterslice semiconductor device. That is, thirdly, the electric power consumption of the masterslice semiconductor device should be reduced. Fourthly, the types of logic circuits should further offer a large variety. Fifthly, the length of the metal wiring on the special masterslice semiconductor device should be shortened. The reasons why the above mentioned third through fifth requirements have arisen will be explained hereinafter.